On Mon, Aug 18, 2025 at 02:16:16PM GMT, Shradha Todi wrote: > > > + > > > + phys: > > > + maxItems: 1 > > > + > > > + samsung,syscon-pcie: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: phandle for system control registers, used to > > > + control signals at system level > > > > What is "system level"? and what are these "signals" being controlled? > > > > I will add a more detailed description for why the syscon is being used > > > > > > +title: Tesla FSD SoC series PCIe Host Controller > > > + > > > +maintainers: > > > + - Shradha Todi <shradha.t@xxxxxxxxxxx> > > > + > > > +description: > > > + Tesla FSD SoCs PCIe host controller inherits all the common > > > + properties defined in samsung,exynos-pcie.yaml > > > + > > > +allOf: > > > + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# > > > + > > > +properties: > > > + compatible: > > > + const: tesla,fsd-pcie > > > + > > > + clocks: > > > + maxItems: 4 > > > + > > > + clock-names: > > > + items: > > > + - const: aux > > > + - const: dbi > > > + - const: mstr > > > + - const: slv > > > + > > > + num-lanes: > > > + maximum: 4 > > > + > > > + samsung,syscon-pcie: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: phandle for system control registers, used to > > > + control signals at system level > > > + > > > +required: > > > + - samsung,syscon-pcie > > > > clocks are required, compatible as well. > > > > Since this was inheriting the common exynos yaml file and that had these properties > under required, I did not mention again. Will take care in next version. > dma-coherent needs to be a required property as well since this binding is supporting only one controller, that seem to have cache coherent DMA. > > Missing supplies, both as properties and required. PCI devices do not > > work without power. > > > > According to the HW design of FSD SoC, the control to manage PCIe power is given to > a separate CPU where custom firmware runs. Therefore, the Linux side does not control > the PCIe power supplies directly and are hence not included in the device tree. What do you mean by 'PCIe power'? Supply to the PCIe controller/bus or the devices connected to the bus? - Mani -- மணிவண்ணன் சதாசிவம்
