On Mon, Aug 11, 2025 at 09:16:33PM GMT, Shradha Todi wrote:
> Add Tesla FSD SoC support for both RC and EP.
Add some info about the PCIe controller here. Like the data rate supported,
lanes, interrupts, any quirks etc...
>
> Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx>
> ---
> .../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++
> .../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++
> 2 files changed, 168 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
>
[...]
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/fsd-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcierc1: pcie@16b00000 {
> + compatible = "tesla,fsd-pcie";
> + reg = <0x0 0x16b00000 0x0 0x2000>,
> + <0x0 0x168c0000 0x0 0x1000>,
> + <0x0 0x18000000 0x0 0x1000>;
> + reg-names = "dbi", "elbi", "config";
> + ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
> + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
> + clock-names = "aux", "dbi", "mstr", "slv";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + device_type = "pci";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
Only one SPI interrupt? What about INTx? Don't you have any external/internal
MSI controller?
- Mani
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