Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 31 March 2025 20:05
> Subject: Re: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support
>
> Hi Biju,
>
> On Mon, 31 Mar 2025 at 20:29, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Mon, 31 Mar 2025
> > > at 17:33, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Mon, 31 Mar
> > > > > 2025 at 16:34, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > > > > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Mon, 31
> > > > > > > Mar
> > > > > > > 2025 at 15:54, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > > > > > > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Document
> > > > > > > > > support for the Expanded Serial Peripheral Interface
> > > > > > > > > (xSPI) Controller in the Renesas RZ/G3E
> > > > > > > > > (R9A09G047) SoC.
> > > > > > > > >
> > > > > > > > > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > > > > >
> > > > > > > > > --- /dev/null
> > > > > > > > > +++ b/Documentation/devicetree/bindings/memory-controlle
> > > > > > > > > +++ rs/r
> > > > > > > > > +++ enes
> > > > > > > > > +++ as,r
> > > > > > > > > +++ zg3e
> > > > > > > > > +++ -xspi.yaml
> > > > > > >
> > > > > > > > > + spi@11030000 {
> > > > > > > > > + compatible = "renesas,r9a09g047-xspi";
> > > > > > > > > + reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
> > > > > > > > > + reg-names = "regs", "dirmap";
> > > > > > > > > + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > > > > > > > > + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > > > > > > > > + interrupt-names = "pulse", "err_pulse";
> > > > > > > > > + clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
> > > > > > > > > + <&cpg CPG_MOD 0xa1>, <&cpg CPG_MOD
> > > > > > > > > + 0xa1>;
> > > > > > > >
> > > > > > > > On the next version I am going to update spix2 clk as
> > > > > > > > <&cpg CPG_CORE R9A09G047_SPI_CLK_SPIX2>
> > >
> > > According to the RZ/G3E clock system diagram, (the parent of)
> > > clk_spi is derived from (the parent of) clk_spix2, not the other way around?
> > > So you can model clk_spi as a fixed divider clock with parent
> > > clk_spix2 and factor two. I.e. provide a new core clock R9A09G047_SPI_CLK_SPI instead of your
> proposed R9A09G047_SPI_CLK_SPIX2?
> ^^^^
OK.
>
> > > > > > > What's spix2 clk? Ah, re-adding dropped line:
> > > > > > >
> > > > > > > > > + clock-names = "ahb", "axi", "spi", "spix2";
>
> > Can you please share your thoughts to handle this?
>
> See above ^^^^ ;-)
>
> > 1) Gate only spi clk
>
> Gate only clk_spix2, which is the parent of clk_spi.
> So enabling any of them will (propagate to) enable clk_spix2, which uses the hardware gate.
Agreed.
>
> > 2) For monitoring use both clock
>
> Check only clk_spix2 for monitoring.
Ok.
>
> > 3) Clock specifier needs two distinct entries. So that consumer will get
> > proper rates for both clocks.
>
> clk_spi would be a separate fixed-divider clock.
Agreed.
Cheers,
Biju
