RE: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support

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Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 31 March 2025 15:12
> Subject: Re: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support
> 
> Hi Biju,
> 
> On Mon, 31 Mar 2025 at 15:54, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Document support for the
> > > Expanded Serial Peripheral Interface (xSPI) Controller in the
> > > Renesas RZ/G3E
> > > (R9A09G047) SoC.
> > >
> > > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,r
> > > +++ zg3e
> > > +++ -xspi.yaml
> 
> > > +    spi@11030000 {
> > > +        compatible = "renesas,r9a09g047-xspi";
> > > +        reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
> > > +        reg-names = "regs", "dirmap";
> > > +        interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > > +                     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > > +        interrupt-names = "pulse", "err_pulse";
> > > +        clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
> > > +                 <&cpg CPG_MOD 0xa1>, <&cpg CPG_MOD 0xa1>;
> >
> > On the next version I am going to update spix2 clk as <&cpg CPG_CORE
> > R9A09G047_SPI_CLK_SPIX2>
> 
> What's spix2 clk? Ah, re-adding dropped line:
> 
> > > +        clock-names = "ahb", "axi", "spi", "spix2";
> 
> > Based on [1], the clk specifier cannot distinguish between spi and
> > spix2 clk, as entries are same(gating bits). So, treating
> > spix2 as core clock to distinguish them.
> >
> > Please let me know if there are any issues in this approach?
> 
> As you wrote in [2], you have to check the two monitor register bits together. How do you plan to
> handle that requirement?

As per hardware team, spix2 clock is twice the frequency of the spi clock, and the clock ON/OFF period
displayed for each bit in the monitor register varies slightly due to the difference in frequency. 

So, if I monitor the bit of slowest clock(spi) that will confirm both right?

Cheers,
Biju

> 
> > [1]
> > https://lore.kernel.org/all/TY3PR01MB11346B3B6CFF1359411B475A386A62@TY
> > 3PR01MB11346.jpnprd01.prod.outlook.com/
> 
> [2]
> https://lore.kernel.org/all/TY3PR01MB11346D2881A8CC9C3019C978386D22@xxxxxxxxxxxxxxxxxxxxxxxxxxxx.outlo
> ok.com
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds




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