RE: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support

[Biju Das <biju.das.jz@xxxxxxxxxxxxxx>]

Hi All,

> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 11 March 2025 11:36
> Subject: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support
> 
> Document support for the Expanded Serial Peripheral Interface (xSPI) Controller in the Renesas RZ/G3E
> (R9A09G047) SoC.
> 
> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * As rz-xspi is too generic, replaced file name rz-xspi->rzg3e-xspi
>    and dropped generic compatible rz-xspi.
>  * Dropped prefix spi from interrupt names.
>  * Updated the example with above changes.
>  * Retained Rb tag from Rob as these changes are trivial.
> ---
>  .../renesas,rzg3e-xspi.yaml                   | 135 ++++++++++++++++++
>  1 file changed, 135 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
> new file mode 100644
> index 000000000000..4d5aa5812d74
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e
> +++ -xspi.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id:
> +http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yam
> +l#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas Expanded Serial Peripheral Interface (xSPI)
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> +
> +description: |
> +  Renesas xSPI allows a SPI flash connected to the SoC to be accessed
> +via
> +  the memory-mapping or the manual command mode.
> +
> +  The flash chip itself should be represented by a subnode of the XSPI node.
> +  The flash interface is selected based on the "compatible" property of
> + this
> +  subnode:
> +  -  "jedec,spi-nor";
> +
> +allOf:
> +  - $ref: /schemas/spi/spi-controller.yaml#
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g047-xspi  # RZ/G3E
> +
> +  reg:
> +    items:
> +      - description: xSPI registers
> +      - description: direct mapping area
> +
> +  reg-names:
> +    items:
> +      - const: regs
> +      - const: dirmap
> +
> +  interrupts:
> +    items:
> +      - description: Interrupt pulse signal by factors excluding errors
> +      - description: Interrupt pulse signal by error factors
> +
> +  interrupt-names:
> +    items:
> +      - const: pulse
> +      - const: err_pulse
> +
> +  clocks:
> +    items:
> +      - description: AHB clock
> +      - description: AXI clock
> +      - description: SPI clock
> +      - description: Double speed SPI clock
> +
> +  clock-names:
> +    items:
> +      - const: ahb
> +      - const: axi
> +      - const: spi
> +      - const: spix2
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: Hardware reset
> +      - description: AXI reset
> +
> +  reset-names:
> +    items:
> +      - const: hresetn
> +      - const: aresetn
> +
> +  renesas,xspi-cs-addr-sys:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      Phandle to the system controller (sys) that allows to configure
> +      xSPI CS0 and CS1 addresses.
> +
> +patternProperties:
> +  "flash@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        contains:
> +          const: jedec,spi-nor
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - resets
> +  - reset-names
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +    spi@11030000 {
> +        compatible = "renesas,r9a09g047-xspi";
> +        reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
> +        reg-names = "regs", "dirmap";
> +        interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> +        interrupt-names = "pulse", "err_pulse";
> +        clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
> +                 <&cpg CPG_MOD 0xa1>, <&cpg CPG_MOD 0xa1>;

On the next version I am going to update spix2 clk as
<&cpg CPG_CORE R9A09G047_SPI_CLK_SPIX2>

Based on [1], the clk specifier cannot distinguish between
spi and spix2 clk, as entries are same(gating bits). So, treating
spix2 as core clock to distinguish them.

Please let me know if there are any issues in this approach?

[1] https://lore.kernel.org/all/TY3PR01MB11346B3B6CFF1359411B475A386A62@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/

Cheers,
Biju

> +        clock-names = "ahb", "axi", "spi", "spix2";
> +        power-domains = <&cpg>;
> +        resets = <&cpg 0xa3>, <&cpg 0xa4>;
> +        reset-names = "hresetn", "aresetn";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        flash@0 {
> +          compatible = "jedec,spi-nor";
> +          reg = <0>;
> +          spi-max-frequency = <40000000>;
> +          spi-tx-bus-width = <1>;
> +          spi-rx-bus-width = <1>;
> +        };
> +    };
> --
> 2.43.0