Hi Biju,
On Mon, 31 Mar 2025 at 15:54, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Document support for the Expanded Serial Peripheral Interface (xSPI) Controller in the Renesas RZ/G3E
> > (R9A09G047) SoC.
> >
> > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e
> > +++ -xspi.yaml
> > + spi@11030000 {
> > + compatible = "renesas,r9a09g047-xspi";
> > + reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
> > + reg-names = "regs", "dirmap";
> > + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "pulse", "err_pulse";
> > + clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
> > + <&cpg CPG_MOD 0xa1>, <&cpg CPG_MOD 0xa1>;
>
> On the next version I am going to update spix2 clk as
> <&cpg CPG_CORE R9A09G047_SPI_CLK_SPIX2>
What's spix2 clk? Ah, re-adding dropped line:
> > + clock-names = "ahb", "axi", "spi", "spix2";
> Based on [1], the clk specifier cannot distinguish between
> spi and spix2 clk, as entries are same(gating bits). So, treating
> spix2 as core clock to distinguish them.
>
> Please let me know if there are any issues in this approach?
As you wrote in [2], you have to check the two monitor register bits
together. How do you plan to handle that requirement?
> [1] https://lore.kernel.org/all/TY3PR01MB11346B3B6CFF1359411B475A386A62@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
[2] https://lore.kernel.org/all/TY3PR01MB11346D2881A8CC9C3019C978386D22@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
