Hi Geert,
On Mon, Apr 28, 2025 at 2:36 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, 28 Apr 2025 at 15:22, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > On Tue, Apr 15, 2025 at 3:55 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > >
> > > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > > used as clock sources for the GBETH IP.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > ---
> > > > drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
> > > > drivers/clk/renesas/rzv2h-cpg.h | 11 +++++
> > > > 2 files changed, 83 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > index 3c40e36259fe..057bfa0e2a57 100644
> > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > >
> > > > @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> > > > DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> > > > DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
> > > >
> > > > + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> > > > + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> > > > + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> > > > + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> > > > + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> > > > + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> > > > + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> > > > + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> > > > + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> > > > + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> > > > +
> > > > DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
> > > >
> > > > /* Core Clocks */
> > >
> > > > @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> > > > BUS_MSTOP(7, BIT(10))),
> > > > DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
> > > > BUS_MSTOP(7, BIT(11))),
> > > > + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> > > > + BUS_MSTOP(8, BIT(5)),
> > > > + 0x300, 8, 1),
> > >
> > > CPG_SSEL0
> > >
> > > I'm wondering if you really have to store and duplicate this info here.
> > > Can't you infer it from the parent's smux description?
> > >
> > To clarify, you mean to get the parent of the mod clock and then get
> > the clk_mux to get the base?
>
> Indeed.
>
Thank you for the clarification.
Cheers,
Prabhakar
