Hi Prabhakar,
On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add clock and reset entries for GBETH instances. Include core clocks for
> PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> used as clock sources for the GBETH IP.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
> drivers/clk/renesas/rzv2h-cpg.h | 11 +++++
> 2 files changed, 83 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> index 3c40e36259fe..057bfa0e2a57 100644
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
>
> + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> +
> DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
>
> /* Core Clocks */
> @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> BUS_MSTOP(7, BIT(10))),
> DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
> BUS_MSTOP(7, BIT(11))),
> + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> + BUS_MSTOP(8, BIT(5)),
> + 0x300, 8, 1),
CPG_SSEL0
I'm wondering if you really have to store and duplicate this info here.
Can't you infer it from the parent's smux description?
> + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> + BUS_MSTOP(8, BIT(5)),
> + 0x300, 12, 1),
> + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
> + BUS_MSTOP(8, BIT(5)),
> + 0x300, 8, 1),
> + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
> + BUS_MSTOP(8, BIT(5)),
> + 0x300, 12, 1),
> + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
> + BUS_MSTOP(8, BIT(6)),
> + 0x304, 8, 1),
CPG_SSEL0
> + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
> + BUS_MSTOP(8, BIT(6)),
> + 0x304, 12, 1),
> + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
> + BUS_MSTOP(8, BIT(6)),
> + 0x304, 8, 1),
> + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
> + BUS_MSTOP(8, BIT(6)),
> + 0x304, 12, 1),
> + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> + BUS_MSTOP(8, BIT(6))),
> DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> BUS_MSTOP(9, BIT(4))),
> DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
> @@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
> DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
> DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
> DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
> + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
> + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
> DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
> DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
> DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index c64cfead6dc1..e730179d92aa 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -93,10 +93,13 @@ struct smuxed {
> .width = (_width), \
> })
>
> +#define CPG_SSEL0 (0x300)
> +#define CPG_SSEL1 (0x304)
> #define CPG_CDDIV0 (0x400)
> #define CPG_CDDIV1 (0x404)
> #define CPG_CDDIV3 (0x40C)
> #define CPG_CDDIV4 (0x410)
> +#define CPG_CSDIV0 (0x500)
>
> #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
> #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
> @@ -111,6 +114,14 @@ struct smuxed {
> #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
> #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
>
> +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
> +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
> +
> +#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
> +#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
> +#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1)
> +#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
> +
> #define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
> #define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
> #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
