From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
This patch series adds initial support for the Renesas RZ/V2N (R9A09G056)
SoC and its evaluation board (EVK). The Renesas RZ/V2N is a vision AI
microprocessor (MPU) designed for power-efficient AI inference and
real-time vision processing. It features Renesas' proprietary AI
accelerator (DRP-AI3), delivering up to 15 TOPS AI performance, making
it ideal for applications such as Driver Monitoring Systems (DMS),
industrial monitoring cameras, and mobile robots.
Key features of the RZ/V2N SoC:
Processing Power:
- Quad Arm Cortex-A55 cores at 1.8GHz for high-performance computing
- Single Arm Cortex-M33 core at 200MHz for real-time processing
- 1.5MB on-chip SRAM for fast data access
- LPDDR4/LPDDR4X memory interface for high-speed RAM access
AI and Vision Processing:
- DRP-AI3 accelerator for low-power, high-efficiency AI inference
- Arm Mali-C55 ISP (optional) for image signal processing
- Dual MIPI CSI-2 camera interfaces for multi-camera support
High-Speed Interfaces:
- PCIe Gen3 (2-lane) 1ch for external device expansion
- USB 3.2 (Gen2) 1ch (Host-only) for high-speed data transfer
- USB 2.0 (Host/Function) 1ch for legacy connectivity
- Gigabit Ethernet (2 channels) for network communication
Industrial and Automotive Features:
- 6x CAN FD channels for automotive and industrial networking
- 24-channel ADC for sensor data acquisition
LINK: https://tinyurl.com/renesas-rz-v2n-soc
The series introduces:
- Device tree bindings for various subsystems (SYS, SCIF, SDHI, CPG, pinctrl).
- RZ/V2N SoC identification support.
- Clock and pinctrl driver updates for RZ/V2N.
- Initial DTSI and device tree for the RZ/V2N SoC and EVK.
These patches have been tested on the RZ/V2N EVK with v6.15-rc1 kernel,
logs can be found here:
https://gist.github.com/prabhakarlad/aa3da7558d007aab8a288550005565d3
@Geert, Ive rebased the patches on top of v6.15-rc1 + renesas-dts-for-v6.16
+ renesas-clk-for-v6.16 branches. Also these patches apply on top of the below
series [1] and [2]. I had to sort the order in Makefile for patch [3] to
avoid conflicts.
[1] https://lore.kernel.org/all/20250401090133.68146-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
[2] https://lore.kernel.org/all/20250403212919.1137670-1-thierry.bultel.yh@xxxxxxxxxxxxxx/#t
[3] https://lore.kernel.org/all/20250403212919.1137670-13-thierry.bultel.yh@xxxxxxxxxxxxxx/
Note, dtbs_check will generate the below warnings this is due to missing
ICU support as part of initial series. I will be sending a follow-up patch
series to add ICU support which will fix these warnings.
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000 (renesas,r9a09g056-pinctrl): 'interrupt-controller' is a required property
from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000 (renesas,r9a09g056-pinctrl): '#interrupt-cells' is a required property
from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
v1->v2:
- Added acks from Rob.
- Squashed the RZ/V2N EVK and SoC variant documentation into a single
commit.
- Updated the commit messages.
- Added RZV2N_Px, RZV2N_PORT_PINMUX, and RZV2N_GPIO macros in
SoC DTSI as we are re-using renesas,r9a09g057-pinctrl.h
in pictrl driver hence to keep the consistency with the
RZ/V2H(P) SoC these macros are added.
- Dropped `renesas,r9a09g056-pinctrl.h` header file.
- Followed DTS coding style guidelines
- Dropped defconfig changes from the series.
- Dropped SDHI dt-binding patch as its already applied to mmc -next tree.
Cheers,
Prabhakar
Lad Prabhakar (12):
dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and
EVK
soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
soc: renesas: sysc: Add SoC identification for RZ/V2N SoC
dt-bindings: serial: renesas: Document RZ/V2N SCIF
dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
clk: renesas: rzv2h-cpg: Sort compatible list based on SoC part number
clk: renesas: rzv2h: Add support for RZ/V2N SoC
dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
.../bindings/clock/renesas,rzv2h-cpg.yaml | 5 +-
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +
.../bindings/serial/renesas,scif.yaml | 1 +
.../soc/renesas/renesas,r9a09g057-sys.yaml | 1 +
.../bindings/soc/renesas/renesas.yaml | 15 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 282 ++++++++++++++++++
.../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 114 +++++++
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a09g056-cpg.c | 152 ++++++++++
drivers/clk/renesas/rzv2h-cpg.c | 18 +-
drivers/clk/renesas/rzv2h-cpg.h | 1 +
drivers/pinctrl/renesas/Kconfig | 1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 36 ++-
drivers/soc/renesas/Kconfig | 11 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r9a09g056-sys.c | 107 +++++++
drivers/soc/renesas/rz-sysc.c | 3 +
drivers/soc/renesas/rz-sysc.h | 1 +
.../dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 ++
21 files changed, 774 insertions(+), 9 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c
create mode 100644 drivers/soc/renesas/r9a09g056-sys.c
create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
--
2.49.0
