On Thu, Apr 24, 2025 at 09:13:54AM GMT, Biju Das wrote: > Add definitions for XSPI core clock and Gigabit Ethernet PTP reference > core clocks in the R9A09G047 CPG DT bindings header file. > > The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and > factor two as both parent and child share same gating bit. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v3: > * New patch Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
