The RZ/G3E XSPI has 4 clocks{ahb, axi, spi, spix2). spi and spix2 clks
share the same CPG_ON bit, but they have different monitor bit.
Modelled clk_spi as a fixed divider clock with parent clk_spix2 and
factor two.
v2->v3:
* Added definitions for XSPI core clock and Gigabit Ethernet PTP
reference core clocks in the R9A09G047 CPG DT bindings header file.
* Updated LAST_DT_CORE_CLK entry.
* Moved "spi_clk_spi" definitions from patch#2 to #3.
v1->v2:
* Modelled clk_spi as a fixed divider clock with parent clk_spix2 and
factor two and dropped coupled clk.
* Updated commit description for the cover letter
* Dropped static divider patch as it is updated as [1]
* Updated LAST_DT_CORE_CLK macro
* Replaced DEF_SDIV->DEF_CSDIV macro
* Added spi_clk_spi as core clk
* Updated CSDIV0_DIVCTL3 macro.
* spi_clk_spix2 is handled as module clock with RPM.
* Dropped CDDIV0_DIVCTL1 as it is already merged in clk tree.
Biju Das (3):
dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core
clocks
clk: renesas: r9a09g047: Add support for xspi mux and divider
clk: renesas: r9a09g047: Add XSPI clock/reset
drivers/clk/renesas/r9a09g047-cpg.c | 39 ++++++++++++++++++-
drivers/clk/renesas/rzv2h-cpg.h | 7 ++++
.../dt-bindings/clock/renesas,r9a09g047-cpg.h | 3 ++
3 files changed, 48 insertions(+), 1 deletion(-)
--
2.43.0
