Hi Andrew,
On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@xxxxxxx> wrote:
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
>
> > miic_reg_writel(miic, MIIC_MODCTRL,
> > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
> You might however want to add a comment that this assumption is being
> made.
I guess Prabhakar did it this way to make it easier to find
candidates for a future conversion to field_prep(), if this ever becomes
available[1].
[1] "[PATCH v3 0/4] Non-const bitfield helpers"
https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@xxxxxxxxx
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
