On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Move the hardcoded switch mode mask definition into the SoC-specific
> miic_of_data structure. This allows each SoC to define its own mask
> value rather than relying on a single fixed constant. For RZ/N1 the
> mask remains GENMASK(4, 0).
>
> This is in preparation for adding support for RZ/T2H, where the
> switch mode mask is GENMASK(2, 0).
> -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
> miic_reg_writel(miic, MIIC_MODCTRL,
> - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
_ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
this __ffs() is pointless.
You might however want to add a comment that this assumption is being
made.
Andrew
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pw-bot: cr
