From: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
Add initial DT support for R8A78000 (R-Car X5H) SoC.
[Kuninori: tidyup for upstreaming]
Signed-off-by: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@xxxxxxxxxxx>
Signed-off-by: Minh Le <minh.le.aj@xxxxxxxxxxx>
Signed-off-by: Huy Bui <huy.bui.wm@xxxxxxxxxxx>
Signed-off-by: Khanh Le <khanh.le.xr@xxxxxxxxxxx>
Signed-off-by: Phong Hoang <phong.hoang.wz@xxxxxxxxxxx>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 1063 +++++++++++++++++++++
1 file changed, 1063 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
new file mode 100644
index 000000000000..165c4e9fcf3b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -0,0 +1,1063 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car X5H (R8A78000) SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r8a78000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a720_0>;
+ };
+ core1 {
+ cpu = <&a720_1>;
+ };
+ core2 {
+ cpu = <&a720_2>;
+ };
+ core3 {
+ cpu = <&a720_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a720_4>;
+ };
+ core1 {
+ cpu = <&a720_5>;
+ };
+ core2 {
+ cpu = <&a720_6>;
+ };
+ core3 {
+ cpu = <&a720_7>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&a720_8>;
+ };
+ core1 {
+ cpu = <&a720_9>;
+ };
+ core2 {
+ cpu = <&a720_10>;
+ };
+ core3 {
+ cpu = <&a720_11>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&a720_12>;
+ };
+ core1 {
+ cpu = <&a720_13>;
+ };
+ core2 {
+ cpu = <&a720_14>;
+ };
+ core3 {
+ cpu = <&a720_15>;
+ };
+ };
+
+ cluster4 {
+ core0 {
+ cpu = <&a720_16>;
+ };
+ core1 {
+ cpu = <&a720_17>;
+ };
+ core2 {
+ cpu = <&a720_18>;
+ };
+ core3 {
+ cpu = <&a720_19>;
+ };
+ };
+
+ cluster5 {
+ core0 {
+ cpu = <&a720_20>;
+ };
+ core1 {
+ cpu = <&a720_21>;
+ };
+ core2 {
+ cpu = <&a720_22>;
+ };
+ core3 {
+ cpu = <&a720_23>;
+ };
+ };
+
+ cluster6 {
+ core0 {
+ cpu = <&a720_24>;
+ };
+ core1 {
+ cpu = <&a720_25>;
+ };
+ core2 {
+ cpu = <&a720_26>;
+ };
+ core3 {
+ cpu = <&a720_27>;
+ };
+ };
+
+ cluster7 {
+ core0 {
+ cpu = <&a720_28>;
+ };
+ core1 {
+ cpu = <&a720_29>;
+ };
+ core2 {
+ cpu = <&a720_30>;
+ };
+ core3 {
+ cpu = <&a720_31>;
+ };
+ };
+ };
+
+ a720_0: cpu@0 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x0>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_0>;
+ enable-method = "psci";
+
+ L1_CA720_0: controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_0>;
+ };
+
+ L2_CA720_0: controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_0>;
+ };
+ };
+
+ a720_1: cpu@100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_1>;
+ enable-method = "psci";
+
+ L1_CA720_1: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_1>;
+ };
+
+ L2_CA720_1: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_0>;
+ };
+ };
+
+ a720_2: cpu@200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_2>;
+ enable-method = "psci";
+
+ L1_CA720_2: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_2>;
+ };
+
+ L2_CA720_2: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_0>;
+ };
+ };
+
+ a720_3: cpu@300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_3>;
+ enable-method = "psci";
+
+ L1_CA720_3: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_3>;
+ };
+
+ L2_CA720_3: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_0>;
+ };
+ };
+
+ a720_4: cpu@10000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x10000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_4>;
+ enable-method = "psci";
+
+ L1_CA720_4: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_4>;
+ };
+
+ L2_CA720_4: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_1>;
+ };
+ };
+
+ a720_5: cpu@10100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x10100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_5>;
+ enable-method = "psci";
+
+ L1_CA720_5: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_5>;
+ };
+
+ L2_CA720_5: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_1>;
+ };
+ };
+
+ a720_6: cpu@10200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x10200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_6>;
+ enable-method = "psci";
+
+ L1_CA720_6: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_6>;
+ };
+
+ L2_CA720_6: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_1>;
+ };
+ };
+
+ a720_7: cpu@10300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x10300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_7>;
+ enable-method = "psci";
+
+ L1_CA720_7: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_7>;
+ };
+
+ L2_CA720_7: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_1>;
+ };
+ };
+
+ a720_8: cpu@20000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x20000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_8>;
+ enable-method = "psci";
+
+ L1_CA720_8: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_8>;
+ };
+
+ L2_CA720_8: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_2>;
+ };
+ };
+
+ a720_9: cpu@20100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x20100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_9>;
+ enable-method = "psci";
+
+ L1_CA720_9: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_9>;
+ };
+
+ L2_CA720_9: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_2>;
+ };
+ };
+
+ a720_10: cpu@20200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x20200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_10>;
+ enable-method = "psci";
+
+ L1_CA720_10: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_10>;
+ };
+
+ L2_CA720_10: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_2>;
+ };
+ };
+
+ a720_11: cpu@20300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x20300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_11>;
+ enable-method = "psci";
+
+ L1_CA720_11: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_11>;
+ };
+
+ L2_CA720_11: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_2>;
+ };
+ };
+
+ a720_12: cpu@30000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x30000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_12>;
+ enable-method = "psci";
+
+ L1_CA720_12: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_12>;
+ };
+
+ L2_CA720_12: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_3>;
+ };
+ };
+
+ a720_13: cpu@30100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x30100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_13>;
+ enable-method = "psci";
+
+ L1_CA720_13: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_13>;
+ };
+
+ L2_CA720_13: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_3>;
+ };
+ };
+
+ a720_14: cpu@30200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x30200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_14>;
+ enable-method = "psci";
+
+ L1_CA720_14: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_14>;
+ };
+
+ L2_CA720_14: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_3>;
+ };
+ };
+
+ a720_15: cpu@30300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x30300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_15>;
+ enable-method = "psci";
+
+ L1_CA720_15: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_15>;
+ };
+
+ L2_CA720_15: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_3>;
+ };
+ };
+
+ a720_16: cpu@40000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x40000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_16>;
+ enable-method = "psci";
+
+ L1_CA720_16: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_16>;
+ };
+
+ L2_CA720_16: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_4>;
+ };
+ };
+
+ a720_17: cpu@40100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x40100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_17>;
+ enable-method = "psci";
+
+ L1_CA720_17: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_17>;
+ };
+
+ L2_CA720_17: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_4>;
+ };
+ };
+
+ a720_18: cpu@40200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x40200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_18>;
+ enable-method = "psci";
+
+ L1_CA720_18: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_18>;
+ };
+
+ L2_CA720_18: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_4>;
+ };
+ };
+
+ a720_19: cpu@40300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x40300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_19>;
+ enable-method = "psci";
+
+ L1_CA720_19: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_19>;
+ };
+
+ L2_CA720_19: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_4>;
+ };
+ };
+
+ a720_20: cpu@50000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x50000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_20>;
+ enable-method = "psci";
+
+ L1_CA720_20: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_20>;
+ };
+
+ L2_CA720_20: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_5>;
+ };
+ };
+
+ a720_21: cpu@50100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x50100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_21>;
+ enable-method = "psci";
+
+ L1_CA720_21: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_21>;
+ };
+
+ L2_CA720_21: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_5>;
+ };
+ };
+
+ a720_22: cpu@50200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x50200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_22>;
+ enable-method = "psci";
+
+ L1_CA720_22: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_22>;
+ };
+
+ L2_CA720_22: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_5>;
+ };
+ };
+
+ a720_23: cpu@50300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x50300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_23>;
+ enable-method = "psci";
+
+ L1_CA720_23: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_23>;
+ };
+
+ L2_CA720_23: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_5>;
+ };
+ };
+
+ a720_24: cpu@60000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x60000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_24>;
+ enable-method = "psci";
+
+ L1_CA720_24: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_24>;
+ };
+
+ L2_CA720_24: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_6>;
+ };
+ };
+
+ a720_25: cpu@60100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x60100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_25>;
+ enable-method = "psci";
+
+ L1_CA720_25: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_25>;
+ };
+
+ L2_CA720_25: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_6>;
+ };
+ };
+
+ a720_26: cpu@60200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x60200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_26>;
+ enable-method = "psci";
+
+ L1_CA720_26: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_26>;
+ };
+
+ L2_CA720_26: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_6>;
+ };
+ };
+
+ a720_27: cpu@60300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x60300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_27>;
+ enable-method = "psci";
+
+ L1_CA720_27: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_27>;
+ };
+
+ L2_CA720_27: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_6>;
+ };
+ };
+
+ a720_28: cpu@70000 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x70000>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_28>;
+ enable-method = "psci";
+
+ L1_CA720_28: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_28>;
+ };
+
+ L2_CA720_28: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_7>;
+ };
+ };
+
+ a720_29: cpu@70100 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x70100>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_29>;
+ enable-method = "psci";
+
+ L1_CA720_29: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_29>;
+ };
+
+ L2_CA720_29: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_7>;
+ };
+ };
+
+ a720_30: cpu@70200 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x70200>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_30>;
+ enable-method = "psci";
+
+ L1_CA720_30: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_30>;
+ };
+
+ L2_CA720_30: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_7>;
+ };
+ };
+
+ a720_31: cpu@70300 {
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x70300>;
+ device_type = "cpu";
+ next-level-cache = <&L1_CA720_31>;
+ enable-method = "psci";
+
+ L1_CA720_31: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <1>;
+ next-level-cache = <&L2_CA720_31>;
+ };
+
+ L2_CA720_31: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ next-level-cache = <&L3_CA720_7>;
+ };
+ };
+
+ L3_CA720_0: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_1: cache-controller-1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_2: cache-controller-2 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_3: cache-controller-3 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_4: cache-controller-4 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_5: cache-controller-5 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_6: cache-controller-6 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA720_7: cache-controller-7 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <3>;
+ };
+ };
+
+ extal_clk: clock-extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* clock-frequency must be set on board */
+ };
+
+ extalr_clk: clock-extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* clock-frequency must be set on board */
+ };
+
+ /*
+ * In the early phase, there is no clock control support,
+ * so assume that the clocks are enabled by default.
+ * Therefore, dummy clocks are used.
+ */
+ dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <266660000>;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: clock-scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* clock-frequency must be set on board */
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ prr: chipid@189e0044 {
+ compatible = "renesas,prr";
+ reg = <0 0x189e0044 0 4>;
+ };
+
+ /* The Arm GIC-700AE - View 1 */
+ gic: interrupt-controller@39000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x40000>;
+ #redistributor-regions = <32>;
+ reg = <0 0x39000000 0 0x20000>, // GICD
+ <0 0x39080000 0 0x40000>, // GICR Core0
+ <0 0x390C0000 0 0x40000>, // GICR Core1
+ <0 0x39100000 0 0x40000>, // GICR Core2
+ <0 0x39140000 0 0x40000>, // GICR Core3
+ <0 0x39180000 0 0x40000>, // GICR Core4
+ <0 0x391C0000 0 0x40000>, // GICR Core5
+ <0 0x39200000 0 0x40000>, // GICR Core6
+ <0 0x39240000 0 0x40000>, // GICR Core7
+ <0 0x39280000 0 0x40000>, // GICR Core8
+ <0 0x392C0000 0 0x40000>, // GICR Core9
+ <0 0x39300000 0 0x40000>, // GICR Core10
+ <0 0x39340000 0 0x40000>, // GICR Core11
+ <0 0x39380000 0 0x40000>, // GICR Core12
+ <0 0x393C0000 0 0x40000>, // GICR Core13
+ <0 0x39400000 0 0x40000>, // GICR Core14
+ <0 0x39440000 0 0x40000>, // GICR Core15
+ <0 0x39480000 0 0x40000>, // GICR Core16
+ <0 0x394C0000 0 0x40000>, // GICR Core17
+ <0 0x39500000 0 0x40000>, // GICR Core18
+ <0 0x39540000 0 0x40000>, // GICR Core19
+ <0 0x39580000 0 0x40000>, // GICR Core20
+ <0 0x395C0000 0 0x40000>, // GICR Core21
+ <0 0x39600000 0 0x40000>, // GICR Core22
+ <0 0x39640000 0 0x40000>, // GICR Core23
+ <0 0x39680000 0 0x40000>, // GICR Core24
+ <0 0x396C0000 0 0x40000>, // GICR Core25
+ <0 0x39700000 0 0x40000>, // GICR Core26
+ <0 0x39740000 0 0x40000>, // GICR Core27
+ <0 0x39780000 0 0x40000>, // GICR Core28
+ <0 0x397C0000 0 0x40000>, // GICR Core29
+ <0 0x39800000 0 0x40000>, // GICR Core30
+ <0 0x39840000 0 0x40000>; // GICR Core31
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ scif0: serial@c0700000 {
+ compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+ reg = <0 0xc0700000 0 0x40>;
+ interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ scif1: serial@c0704000 {
+ compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+ reg = <0 0xc0704000 0 0x40>;
+ interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ scif3: serial@c0708000 {
+ compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+ reg = <0 0xc0708000 0 0x40>;
+ interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ scif4: serial@c070c000 {
+ compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+ reg = <0 0xc070c000 0 0x40>;
+ interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ hscif0: serial@c0710000 {
+ compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+ reg = <0 0xc0710000 0 0x60>;
+ interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ hscif1: serial@c0714000 {
+ compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+ reg = <0 0xc0714000 0 0x60>;
+ interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ hscif2: serial@c0718000 {
+ compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+ reg = <0 0xc0718000 0 0x60>;
+ interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+
+ hscif3: serial@c071c000 {
+ compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+ reg = <0 0xc071c000 0 0x60>;
+ interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
+ };
+};
--
2.43.0
