Hi Morimoto-san,
On Wed, 10 Sept 2025 at 04:01, Kuninori Morimoto
<kuninori.morimoto.gx@xxxxxxxxxxx> wrote:
> From: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
>
> Add initial DT support for R8A78000 (R-Car X5H) SoC.
>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@xxxxxxxxxxx>
> Signed-off-by: Minh Le <minh.le.aj@xxxxxxxxxxx>
> Signed-off-by: Huy Bui <huy.bui.wm@xxxxxxxxxxx>
> Signed-off-by: Khanh Le <khanh.le.xr@xxxxxxxxxxx>
> Signed-off-by: Phong Hoang <phong.hoang.wz@xxxxxxxxxxx>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> + a720_0: cpu@0 {
> + compatible = "arm,cortex-a720";
"arm,cortex-a720ae"?
> + reg = <0x0 0x0>;
> + device_type = "cpu";
> + next-level-cache = <&L1_CA720_0>;
> + enable-method = "psci";
Please drop this line, as there is no psci node yet.
> +
> + L1_CA720_0: controller-0 {
cache-controller (lots of places).
> + compatible = "cache";
> + cache-unified;
The L1 cache is not unified, according to the documentation?
> + cache-level = <1>;
dtschema/schemas/cache-controller.yaml says valid values are 2..32,
so I think you just have to ignore the L1 cache.
I.e. drop it from DTS, and let the CPU's next-level-cache point to
the L2 cache.
> + next-level-cache = <&L2_CA720_0>;
> + };
> +
> + L2_CA720_0: controller-1 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + next-level-cache = <&L3_CA720_0>;
> + };
Shouldn't this node be located outside the cpu@0 node?
> + };
> +
> + extal_clk: clock-extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* clock-frequency must be set on board */
> + };
> +
> + extalr_clk: clock-extalr {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* clock-frequency must be set on board */
> + };
> +
> + /*
> + * In the early phase, there is no clock control support,
> + * so assume that the clocks are enabled by default.
> + * Therefore, dummy clocks are used.
> + */
> + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
Perhaps use clock-*, for consistency with extal(r)?
However, please note that so far no Renesas DTS files use "clock-*"
as a node name, but "*-clk" is in active use. Krzysztof?
And don't forget to say "Thank you!" to our SCMI overlords ;-)
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <266660000>;
> + };
> +
> + /* External SCIF clock - to be overridden by boards that provide it */
> + scif_clk: clock-scif {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* clock-frequency must be set on board */
This clock is optional, and thus may be left unpopulated on a board,
so please (re-)add "clock-frequency = <0>;".
> + };
> +
> + soc: soc {
> + /* The Arm GIC-700AE - View 1 */
s/700/720/
> + gic: interrupt-controller@39000000 {
> + compatible = "arm,gic-v3";
The documentation states it is compliant with GICv4.1?
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + redistributor-stride = <0x0 0x40000>;
> + #redistributor-regions = <32>;
> + reg = <0 0x39000000 0 0x20000>, // GICD
The base address is 0x38000000, according to the docs?
> + <0 0x39080000 0 0x40000>, // GICR Core0
> + <0 0x390C0000 0 0x40000>, // GICR Core1
> + <0 0x39100000 0 0x40000>, // GICR Core2
> + <0 0x39140000 0 0x40000>, // GICR Core3
> + <0 0x39180000 0 0x40000>, // GICR Core4
> + <0 0x391C0000 0 0x40000>, // GICR Core5
> + <0 0x39200000 0 0x40000>, // GICR Core6
> + <0 0x39240000 0 0x40000>, // GICR Core7
> + <0 0x39280000 0 0x40000>, // GICR Core8
> + <0 0x392C0000 0 0x40000>, // GICR Core9
> + <0 0x39300000 0 0x40000>, // GICR Core10
> + <0 0x39340000 0 0x40000>, // GICR Core11
> + <0 0x39380000 0 0x40000>, // GICR Core12
> + <0 0x393C0000 0 0x40000>, // GICR Core13
> + <0 0x39400000 0 0x40000>, // GICR Core14
> + <0 0x39440000 0 0x40000>, // GICR Core15
> + <0 0x39480000 0 0x40000>, // GICR Core16
> + <0 0x394C0000 0 0x40000>, // GICR Core17
> + <0 0x39500000 0 0x40000>, // GICR Core18
> + <0 0x39540000 0 0x40000>, // GICR Core19
> + <0 0x39580000 0 0x40000>, // GICR Core20
> + <0 0x395C0000 0 0x40000>, // GICR Core21
> + <0 0x39600000 0 0x40000>, // GICR Core22
> + <0 0x39640000 0 0x40000>, // GICR Core23
> + <0 0x39680000 0 0x40000>, // GICR Core24
> + <0 0x396C0000 0 0x40000>, // GICR Core25
> + <0 0x39700000 0 0x40000>, // GICR Core26
> + <0 0x39740000 0 0x40000>, // GICR Core27
> + <0 0x39780000 0 0x40000>, // GICR Core28
> + <0 0x397C0000 0 0x40000>, // GICR Core29
> + <0 0x39800000 0 0x40000>, // GICR Core30
> + <0 0x39840000 0 0x40000>; // GICR Core31
No GICC, GICH, and GICV?
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + scif0: serial@c0700000 {
> + compatible = "renesas,rcar-gen5-scif", "renesas,scif";
Missing "renesas,scif-r8a78000" (everywhere)
("make dtbs_check" would have told you).
> + reg = <0 0xc0700000 0 0x40>;
> + interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
"fck" on SCIF should be (derived from) SGASYNCD16 (66.666 MHz).
According to the DT bindings, "power-domains" and "resets" are missing.
> + status = "disabled";
> + };
> + hscif0: serial@c0710000 {
> + compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
Missing "renesas,hscif-r8a78000".
> + reg = <0 0xc0710000 0 0x60>;
> + interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
"fck" on HSCIF should be (derived from) SGASYNCD8 (133.33 MHz).
According to the DT bindings, "power-domains" and "resets" are missing.
> + status = "disabled";
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
