Hi Geert,
Thank you for the review.
On Wed, Aug 6, 2025 at 1:57 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing
> > rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a
> > pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit
> > positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR
> > locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded
> > PFC_OEN define and obsolete per-SoC OEN helpers.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>
> > @@ -270,6 +270,7 @@ struct rzg2l_hwcfg {
> > u8 func_base;
> > u8 oen_max_pin;
> > u8 oen_max_port;
> > + bool oen_pwpr_lock;
>
> While u8 and bool do have the same size, please keep the bools grouped
> ogether.
>
Ok, I will move it above `func_base` member.
Cheers,
Prabhakar
