From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
The RZ/G3E pin controller does not advertise PIN_CFG_OEN capability, so
there is no valid mapping for output-enable bits on this SoC. Remove the
oen_read and oen_write callbacks from the RZ/G3E driver data to defer
OEN support until PIN_CFG_OEN support is added.
This is a preparatory change for future unification of OEN handling across
the driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 345ee709363b..cf0b92c661d9 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3340,8 +3340,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
#endif
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
- .oen_read = &rzv2h_oen_read,
- .oen_write = &rzv2h_oen_write,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
--
2.49.0
