Hi Geert,
Thank you for the review.
On Tue, Jul 1, 2025 at 11:24 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > The base address can be accessed via the priv pointer already present in
> > struct pll_clk, making the separate base field redundant. Remove the base
> > member and its assignment.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> i.e. will queue in renesas-clk for v6.17, with s/rzv2h-cpg/rzv2h/.
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
>
> > @@ -230,7 +229,6 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
> > struct rzv2h_cpg_priv *priv,
> > const struct clk_ops *ops)
> > {
> > - void __iomem *base = priv->base;
> > struct device *dev = priv->dev;
> > struct clk_init_data init;
> > const struct clk *parent;
>
> Don't forget to update "clk: renesas: rzv2h-cpg: Add support for DSI clocks" ;-)
>
Thanks for the reminder :-)
Cheers,
Prabhakar
