Hi Prabhakar,
On Tue, 24 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The base address can be accessed via the priv pointer already present in
> struct pll_clk, making the separate base field redundant. Remove the base
> member and its assignment.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.17, with s/rzv2h-cpg/rzv2h/.
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -230,7 +229,6 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
> struct rzv2h_cpg_priv *priv,
> const struct clk_ops *ops)
> {
> - void __iomem *base = priv->base;
> struct device *dev = priv->dev;
> struct clk_init_data init;
> const struct clk *parent;
Don't forget to update "clk: renesas: rzv2h-cpg: Add support for DSI clocks" ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
