Hi Prabhakar,
On Thu, 15 May 2025 at 20:31, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The Renesas RZ/V2H(P) ("R9A09G057") SoC supports 1x channel with OTG/DRD
> and 1x channel with host interface.
>
> Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0 channels
> in R9A09G057 SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -662,6 +662,119 @@ sdhi0_vqmmc: vqmmc-regulator {
> };
> };
>
> + ohci0: usb@15800000 {
Moving above mmc@15c00000 to preserve sort order.
[...]
> +
> sdhi1: mmc@15c10000 {
> compatible = "renesas,sdhi-r9a09g057";
> reg = <0x0 0x15c10000 0 0x10000>;
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-devel for v6.17 with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
