Hi, Rob, On 10.05.2025 00:08, Rob Herring wrote: > On Wed, Apr 30, 2025 at 01:32:32PM +0300, Claudiu wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> >> >> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express >> Base Specification 4.0. It is designed for root complex applications and >> features a single-lane (x1) implementation. Add documentation for it. >> The interrupts, interrupt-names, resets, reset-names, clocks, clock-names >> description were obtained from the hardware manual. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> >> --- >> .../pci/renesas,r9a08g045s33-pcie.yaml | 242 ++++++++++++++++++ >> 1 file changed, 242 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml >> new file mode 100644 >> index 000000000000..354f9c3be139 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml >> @@ -0,0 +1,242 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045s33-pcie.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Renesas RZ/G3S PCIe host controller >> + >> +maintainers: >> + - Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> >> + >> +description: >> + Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification >> + 4.0 and supports up to 5 GT/s (Gen2). >> + >> +properties: >> + compatible: >> + const: renesas,r9a08g045s33-pcie # RZ/G3S >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + items: >> + - description: System error interrupt >> + - description: System error on correctable error interrupt >> + - description: System error on non-fatal error interrupt >> + - description: System error on fatal error interrupt >> + - description: AXI error interrupt >> + - description: INTA interrupt >> + - description: INTB interrupt >> + - description: INTC interrupt >> + - description: INTD interrupt >> + - description: MSI interrupt >> + - description: Link bandwidth interrupt >> + - description: PME interrupt >> + - description: DMA interrupt >> + - description: PCIe event interrupt >> + - description: Message interrupt >> + - description: All interrupts >> + >> + interrupt-names: >> + items: >> + - description: int_serr >> + - description: int_ser_cor >> + - description: int_serr_nonfatal >> + - description: int_serr_fatal >> + - description: axi_err_int >> + - description: inta_rc >> + - description: intb_rc >> + - description: intc_rc >> + - description: intd_rc >> + - description: intmsi_rc > > Isn't every interrupt for the root complex? It is! I just used the names that were available in the hardware manual. I'll drop the "_rc" it in the next version. > >> + - description: int_link_bandwidth >> + - description: int_pm_pme >> + - description: dma_int >> + - description: pcie_evt_int >> + - description: msg_int >> + - description: int_all > > 'int_' or '_int' is redundant (and inconsistent). Drop. OK > >> + >> + clocks: >> + items: >> + - description: System clock >> + - description: PM control clock >> + >> + clock-names: >> + items: >> + - description: aclk >> + - description: clkl1pm > > 'l1pm' or 'pm' OK > >> + >> + resets: >> + items: >> + - description: AXI2PCIe Bridge reset >> + - description: Data link layer/transaction layer reset >> + - description: Transaction layer (ACLK domain) reset >> + - description: Transaction layer (PCLK domain) reset >> + - description: Physical layer reset >> + - description: Configuration register reset >> + - description: Configuration register reset >> + >> + reset-names: >> + items: >> + - description: aresetn >> + - description: rst_b >> + - description: rst_gp_b >> + - description: rst_ps_b >> + - description: rst_rsm_b >> + - description: rst_cfg_b >> + - description: rst_load_b >> + >> + power-domains: >> + maxItems: 1 >> + >> + dma-ranges: >> + description: >> + A single range for the inbound memory region. >> + maxItems: 1 >> + >> + renesas,sysc: >> + description: System controller phandle >> + $ref: /schemas/types.yaml#/definitions/phandle >> + >> + vendor-id: >> + const: 0x1912 >> + >> + device-id: >> + const: 0x0033 >> + >> + legacy-interrupt-controller: >> + description: Interrupt controller node for handling legacy PCI interrupts >> + type: object >> + >> + properties: >> + "#address-cells": >> + const: 0 >> + >> + "#interrupt-cells": >> + const: 1 >> + >> + interrupt-controller: true >> + >> + interrupts: >> + items: >> + - description: INTA interrupt >> + - description: INTB interrupt >> + - description: INTC interrupt >> + - description: INTD interrupt >> + >> + required: >> + - "#address-cells" >> + - "#interrupt-cells" >> + - interrupt-controller >> + - interrupts >> + >> + additionalProperties: false >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - resets >> + - reset-names >> + - interrupts >> + - interrupt-names >> + - interrupt-map >> + - interrupt-map-mask >> + - power-domains >> + - "#address-cells" >> + - "#size-cells" >> + - "#interrupt-cells" >> + - renesas,sysc >> + - vendor-id >> + - device-id >> + >> +allOf: >> + - $ref: /schemas/pci/pci-host-bridge.yaml# >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/r9a08g045-cpg.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + bus { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + gic: interrupt-controller { >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + }; > > Drop. Don't need to show provider nodes for the example. This was needed for the schema to compile with the intx node. > >> + >> + pcie@11e40000 { >> + compatible = "renesas,r9a08g045s33-pcie"; >> + reg = <0 0x11e40000 0 0x10000>; >> + ranges = <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; >> + dma-ranges = <0x42000000 0 0x48000000 0 0x48000000 0 0x8000000>; >> + bus-range = <0x0 0xff>; >> + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, >> + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; >> + clock-names = "aclk", "clkl1pm"; >> + resets = <&cpg R9A08G045_PCI_ARESETN>, >> + <&cpg R9A08G045_PCI_RST_B>, >> + <&cpg R9A08G045_PCI_RST_GP_B>, >> + <&cpg R9A08G045_PCI_RST_PS_B>, >> + <&cpg R9A08G045_PCI_RST_RSM_B>, >> + <&cpg R9A08G045_PCI_RST_CFG_B>, >> + <&cpg R9A08G045_PCI_RST_LOAD_B>; >> + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", >> + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; >> + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > > It is very odd that you have the INTx interrupts here and below. > > As I mentioned in the driver, you don't need the legacy node any more. > Just add 'interrupt-controller' to this node and point interrupt-map to > this node. Will try it like this. Thank you for your review, Claudiu > >> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "int_serr", "int_serr_cor", "int_serr_nonfatal", >> + "int_serr_fatal", "axi_err_int", "inta_rc", >> + "intb_rc", "intc_rc", "intd_rc", >> + "intmsi_rc", "int_link_bandwidth", "int_pm_pme", >> + "dma_int", "pcie_evt_int", "msg_int", >> + "int_all"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &pcie_intx 0>, /* INT A */ >> + <0 0 0 2 &pcie_intx 1>, /* INT B */ >> + <0 0 0 3 &pcie_intx 2>, /* INT C */ >> + <0 0 0 4 &pcie_intx 3>; /* INT D */ >> + device_type = "pci"; >> + num-lanes = <1>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + power-domains = <&cpg>; >> + renesas,sysc = <&sysc>; >> + vendor-id = <0x1912>; >> + device-id = <0x0033>; >> + >> + pcie_intx: legacy-interrupt-controller { >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + #address-cells = <0>; >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + }; >> + >> +... >> -- >> 2.43.0 >>
