From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Hi,
Series adds a PCIe driver for the Renesas RZ/G3S SoC.
It is split as follows:
- patch 1/8: updates the max register offset for RZ/G3S SYSC;
this is necessary as the PCIe need to setup the
SYSC for proper functioning
- patch 2/8: adds clock, reset and power domain support for
the PCIe IP
- patch 3/8: exports of_irq_count() symbol; this is used by the
proposed driver to get the number of INTx interrupts
- patches 4-5/8: add PCIe support for the RZ/G3S SoC
- patches 6-8/8: add device tree support
Please provide your feedback.
Merge strategy, if any:
- patches 1-2,6-8/8 can go through the Renesas tree
- patches 4-5/8 can go through the PCI tree; these depends on patch 3/8,
proper sync will be needed b/w PCI tree and Rob's tree
Thank you,
Claudiu Beznea
Claudiu Beznea (8):
soc: renesas: r9a08g045-sysc: Add max reg offset
clk: renesas: r9a08g045: Add clocks, resets and power domain support
for the PCIe
of/irq: Export of_irq_count()
dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the
PCIe IP on Renesas RZ/G3S
PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC
arm64: dts: renesas: r9a08g045s33: Add PCIe node
arm64: dts: renesas: rzg3s-smarc: Enable PCIe
arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC
.../pci/renesas,r9a08g045s33-pcie.yaml | 242 +++
MAINTAINERS | 8 +
arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 70 +
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 11 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a08g045-cpg.c | 19 +
drivers/of/irq.c | 1 +
drivers/pci/controller/Kconfig | 7 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-rzg3s-host.c | 1561 +++++++++++++++++
drivers/soc/renesas/r9a08g045-sysc.c | 1 +
11 files changed, 1922 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml
create mode 100644 drivers/pci/controller/pcie-rzg3s-host.c
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2.43.0
