From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
The RZ/G3S SoC has a variant (R9A08G045S33) which support PCIe. Add the
PCIe node.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi
index 3351f26c7a2a..d8e1dc80e56e 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi
@@ -12,3 +12,73 @@
/ {
compatible = "renesas,r9a08g045s33", "renesas,r9a08g045";
};
+
+&soc {
+ pcie: pcie@11e40000 {
+ compatible = "renesas,r9a08g045s33-pcie";
+ reg = <0 0x11e40000 0 0x10000>;
+ ranges = <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>;
+ dma-ranges = <0x42000000 0 0x48000000 0 0x48000000 0 0x38000000>;
+ bus-range = <0x0 0xff>;
+ clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
+ <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
+ clock-names = "aclk", "clkl1pm";
+ resets = <&cpg R9A08G045_PCI_ARESETN>,
+ <&cpg R9A08G045_PCI_RST_B>,
+ <&cpg R9A08G045_PCI_RST_GP_B>,
+ <&cpg R9A08G045_PCI_RST_PS_B>,
+ <&cpg R9A08G045_PCI_RST_RSM_B>,
+ <&cpg R9A08G045_PCI_RST_CFG_B>,
+ <&cpg R9A08G045_PCI_RST_LOAD_B>;
+ reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
+ "rst_rsm_b", "rst_cfg_b", "rst_load_b";
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int_serr", "int_serr_cor", "int_serr_nonfatal",
+ "int_serr_fatal", "axi_err_int", "inta_rc",
+ "intb_rc", "intc_rc", "intd_rc",
+ "intmsi_rc", "int_link_bandwidth", "int_pm_pme",
+ "dma_int", "pcie_evt_int", "msg_int",
+ "int_all";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intx 0>, /* INT A */
+ <0 0 0 2 &pcie_intx 1>, /* INT B */
+ <0 0 0 3 &pcie_intx 2>, /* INT C */
+ <0 0 0 4 &pcie_intx 3>; /* INT D */
+ device_type = "pci";
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ power-domains = <&cpg>;
+ renesas,sysc = <&sysc>;
+ vendor-id = <0x1912>;
+ device-id = <0x0033>;
+ status = "disabled";
+
+ pcie_intx: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
--
2.43.0
