On Mon, May 12, 2025 at 2:48 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Cheers,
Prabhakar
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index e0ddf8f602c79..a8bcb26f42700 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
> };
>
> l2cache: cache-controller@13400000 {
> - compatible = "andestech,ax45mp-cache", "cache";
> + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> + "cache";
> reg = <0x0 0x13400000 0x0 0x100000>;
> interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
> cache-size = <0x40000>;
> --
> 2.45.2
>
>
