On Mon, May 12, 2025 at 3:12 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
> .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Cheers,
Prabhakar
> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> index d2cbe49f4e15f..82668d327344e 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -28,6 +28,7 @@ select:
> properties:
> compatible:
> items:
> + - const: renesas,r9a07g043f-ax45mp-cache
> - const: andestech,ax45mp-cache
> - const: cache
>
> @@ -70,7 +71,8 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
>
> cache-controller@13400000 {
> - compatible = "andestech,ax45mp-cache", "cache";
> + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> + "cache";
> reg = <0x13400000 0x100000>;
> interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
> cache-line-size = <64>;
> --
> 2.45.2
>
>
