On Mon, May 12, 2025 at 01:05:13PM +0200, Geert Uytterhoeven wrote: > On Mon, 12 May 2025 at 12:05, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > On Mon, May 12, 2025 at 10:59 AM Conor Dooley <conor@xxxxxxxxxx> wrote: > > > On Mon, May 12, 2025 at 11:01:26AM +0200, Geert Uytterhoeven wrote: > > > > On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@xxxxxxxxxx> wrote: > > > > > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > > > > > > > > > When the binding was originally written, it was assumed that all > > > > > ax45mp-caches had the same properties etc. This has turned out to be > > > > > incorrect, as the QiLai SoC has a different number of cache-sets. > > > > > > > > > > Add a specific compatible for the RZ/Five for property enforcement and > > > > > in case there turns out to be additional differences between these > > > > > implementations of the cache controller. > > > > > > > > > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > > > > > > > Thanks for your patch! > > > > > > > > > --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > > > @@ -28,6 +28,7 @@ select: > > > > > properties: > > > > > compatible: > > > > > items: > > > > > + - const: renesas,r9a07g043f-cache > > > > > > > > This name looks a bit too generic to me, as this is not a generic > > > > cache on the R9A07G043F SoC, but specific to the CPU cores. > > > > > > So "reneasas,r9...-cpu-cache"? > > > > Maybe "renesas,r9a07g043f-riscv-cache" ? > > "renesas,r9a07g043f-ax45mp-cache"? > > There don't seem to be many vendor-specific derivatives of standardized > caches, except for "brcm,bcm11351-a2-pl310-cache". The sifive stuff is all "vendor,soc-cache" into "sifive,ccache" but there's little ambiguity about there being an arm version of the same soc there. I don't mind the "renesas,r9...-ax45mp-cache" one you suggested, feels better than "riscv" to me.
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