Hi Conor,
On Fri, 9 May 2025 at 17:39, Conor Dooley <conor@xxxxxxxxxx> wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -28,6 +28,7 @@ select:
> properties:
> compatible:
> items:
> + - const: renesas,r9a07g043f-cache
This name looks a bit too generic to me, as this is not a generic
cache on the R9A07G043F SoC, but specific to the CPU cores.
> - const: andestech,ax45mp-cache
> - const: cache
>
> @@ -70,7 +71,7 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
>
> cache-controller@13400000 {
> - compatible = "andestech,ax45mp-cache", "cache";
> + compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
> reg = <0x13400000 0x100000>;
> interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
> cache-line-size = <64>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
