On Fri, May 09, 2025 at 04:37:57PM +0100, Conor Dooley wrote: > [EXTERNAL MAIL] > > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > When the binding was originally written, it was assumed that all > ax45mp-caches had the same properties etc. This has turned out to be > incorrect, as the QiLai SoC has a different number of cache-sets. > > Add a specific compatible for the RZ/Five for property enforcement and > in case there turns out to be additional differences between these > implementations of the cache controller. > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Acked-by: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
