Hi Daniel,
> From: Dan Scally <dan.scally@xxxxxxxxxxxxxxxx>
> Sent: 08 May 2025 13:30
> Subject: Re: [PATCH 1/4] dt-bindings: clock: Add macros for RZ/V2H ISP clocks
>
> Hi Fabrizio
>
> On 06/05/2025 14:27, Fabrizio Castro wrote:
> > Hi Daniel,
> >
> > Thanks for your patch!
> >
> >> From: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
> >> Sent: 06 May 2025 13:13
> >> Subject: [PATCH 1/4] dt-bindings: clock: Add macros for RZ/V2H ISP clocks
> >>
> >> From: Daniel Scally <dan.scally+renesas@xxxxxxxxxxxxxxxx>
> >>
> >> Add macros for the RZ/V2H ISP clocks so that they can be referred to
> >> descriptively in the drivers.
> > I don't think this patch is needed.
>
>
> Ah, indeed not in this set...I've been using them in the devicetree files (not the drivers as my
> commit message says) for the hardware that consumes the clocks, like so:
>
>
> isp: isp@16080000 {
> compatible = "arm,mali-c55";
> reg = <0 0x16080000 0 0x200000>;
>
> clocks = <&cpg CPG_MOD R9A09G057_ISP0_ACLK>,
> <&cpg CPG_MOD R9A09G057_ISP0_VIN_ACLK>,
> <&cpg CPG_MOD R9A09G057_ISP0_SCLK>;
>
> ...
>
> }
>
>
> Do you think they're useful for those? If so I'll move this and the rest patch to a later series
> that adds those nodes to r9a09g057.dtsi
As you can see from Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml,
we require numbers in the clock cell for `CPG_MOD` clocks. Therefore, the above
snipped would become:
clocks = <&cpg CPG_MOD 0xe2>,
<&cpg CPG_MOD 0xe4>,
<&cpg CPG_MOD 0xe5>;
We only require bindings for `CPG_CORE` clocks, but the above are not `CPG_CORE`
clocks.
If you have a quick scan of the SoC specific .dtsi file you realise that this
is consistent what has been upstreamed so far.
Cheers,
Fab
>
>
> Thanks
>
> Dan
>
>
> >
> > Cheers,
> > Fab
> >
> >> Signed-off-by: Daniel Scally <dan.scally+renesas@xxxxxxxxxxxxxxxx>
> >> ---
> >> include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-
> >> bindings/clock/renesas,r9a09g057-cpg.h
> >> index 541e6d719bd6..cb2ccd9068db 100644
> >> --- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
> >> +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
> >> @@ -17,5 +17,9 @@
> >> #define R9A09G057_CM33_CLK0 6
> >> #define R9A09G057_CST_0_SWCLKTCK 7
> >> #define R9A09G057_IOTOP_0_SHCLK 8
> >> +#define R9A09G057_ISP0_ACLK 226
> >> +#define R9A09G057_ISP0_PCLK 227
> >> +#define R9A09G057_ISP0_VIN_ACLK 228
> >> +#define R9A09G057_ISP0_SCLK 229
> >>
> >> #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
> >> --
> >> 2.34.1
> >>
