Hi Daniel,
Thanks for your patch!
> From: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
> Sent: 06 May 2025 13:13
> Subject: [PATCH 2/4] clk: renesas: r9a09g057-cpg: Add clock entries for RZ/V2H ISP
>
> From: Daniel Scally <dan.scally+renesas@xxxxxxxxxxxxxxxx>
>
> Add the clock entries for the ISP in the RZ/V2H SoC
>
> Signed-off-by: Daniel Scally <dan.scally+renesas@xxxxxxxxxxxxxxxx>
> ---
> drivers/clk/renesas/r9a09g057-cpg.c | 11 +++++++++++
> drivers/clk/renesas/rzv2h-cpg.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> index d63eafbca780..cb001ae5f98b 100644
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -47,6 +47,7 @@ enum clk_ids {
> CLK_PLLVDO_CRU1,
> CLK_PLLVDO_CRU2,
> CLK_PLLVDO_CRU3,
I think you need to rebase this patch on top of the latest changes, as I can see it's
missing `CLK_PLLGPU_GEAR` after `CLK_PLLVDO_CRU3` for example.
> + CLK_PLLVDO_ISP0,
Shall we rename this to CLK_PLLVDO_ISP?
>
> /* Module Clocks */
> MOD_CLK_BASE,
> @@ -110,6 +111,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
>
> + DEF_DDIV(".pllvdo_isp0", CLK_PLLVDO_ISP0, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
s/.pllvdo_isp0/.pllvdo_isp/ ?
The remaining changes look okay to me.
Cheers,
Fab
> +
> /* Core Clocks */
> DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
> DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
> @@ -238,6 +241,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> BUS_MSTOP(9, BIT(7))),
> DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
> BUS_MSTOP(9, BIT(7))),
> + DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
> + BUS_MSTOP(9, BIT(8))),
> + DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
> + BUS_MSTOP(9, BIT(8))),
> + DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
> + BUS_MSTOP(9, BIT(9))),
> + DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP0, 14, 5, 7, 5,
> + BUS_MSTOP(9, BIT(9))),
> };
>
> static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index 576a070763cb..c2e09199a8cd 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -35,6 +35,7 @@ struct ddiv {
>
> #define CPG_CDDIV0 (0x400)
> #define CPG_CDDIV1 (0x404)
> +#define CPG_CDDIV2 (0x408)
> #define CPG_CDDIV3 (0x40C)
> #define CPG_CDDIV4 (0x410)
>
> @@ -44,6 +45,7 @@ struct ddiv {
> #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
> #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
> #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
> +#define CDDIV2_DIVCTL3 DDIV_PACK(CPG_CDDIV2, 12, 3, 11)
> #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
> #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
> #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
> --
> 2.34.1
>
