> From 10µs to 50µs, the clock pulses are part of the recovery sequence. Ahh, that explains. I thought this was all after the recovery. > Around 55µs, the transfer function starts attempting to send data > hence the clock pulse. The short SCL spike around 55us is still strange. However, we might violate t:buf time between STOP and START. Can you please try the attached WIP patch? > The slave device is versa clock geberator 5P35023 (exact part number > on SMARC RZ/G2L 5P35023B-629NLGI) Hmm, G3S has a versa clock generator as well. But I can't find a way to wire GPIO lines to RIIC1 or I2C_PM.
diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index 7ad1ad5c8c3f..42058c789f3f 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -278,6 +278,8 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap) } } + ndelay(RECOVERY_NDELAY / 2); + /* If we can't check bus status, assume recovery worked */ if (ret == -EOPNOTSUPP) ret = 0;
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