On Mon, 7 Apr 2025 at 21:16, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
> SoC Clock Pulse Generator (CPG).
>
> Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
> RZ/V2N SoC and adjust the title and description accordingly.
>
> Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
> constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
> clock driver will be reused for this SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in a branch shared by renesas-clk for v6.16 and
renesas-devel for v6.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
