Hi Geert, Thanks for the feedback. > -----Original Message----- > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Sent: 19 August 2025 16:11 > Subject: Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets > > Hi Biju, > > On Thu, 14 Aug 2025 at 14:48, Biju <biju.das.au@xxxxxxxxx> wrote: > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core > > clocks. The bus clock is module clock and core clock is sourced from > > the bus clock. So add support for module clock as parent reusing the > > existing rzv2h_cpg_fixed_mod_status_clk_register(). > > Thanks for your series! > > > Biju Das (4): > > clk: renesas: rzv2h: Refactor > > rzv2h_cpg_fixed_mod_status_clk_register() > > clk: renesas: rzv2h: Add support for parent mod clocks > > dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks > > clk: renesas: r9a09g047: Add GPT clocks and resets > > I think you are overcomplicating: according to the clock system diagram and clock list sheets, > gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr are really the same clocks (the same is true for rsci_[0- > 9]_pclk and rsci_[0-9]_pclk_sfr). Thanks for correcting me. I got confused with CGC=GPT_0_pclk_sfr for the core clock that made me to complicate the clks. > So you can just describe gpt_[01]_pclk_sfr as normal module clocks, and use them for both the core and > bus blocks in DT, e.g. > > clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; > clock-names = "core", "bus"; > > Do you agree? Yes, I agree. Cheers, Biju
