From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
clocks. The bus clock is module clock and core clock is sourced from
the bus clock. So add support for module clock as parent reusing the
existing rzv2h_cpg_fixed_mod_status_clk_register().
Biju Das (4):
clk: renesas: rzv2h: Refactor
rzv2h_cpg_fixed_mod_status_clk_register()
clk: renesas: rzv2h: Add support for parent mod clocks
dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
clk: renesas: r9a09g047: Add GPT clocks and resets
drivers/clk/renesas/r9a09g047-cpg.c | 10 ++-
drivers/clk/renesas/rzv2h-cpg.c | 74 ++++++++++++-------
drivers/clk/renesas/rzv2h-cpg.h | 22 ++++--
.../dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 +
4 files changed, 75 insertions(+), 33 deletions(-)
--
2.43.0
