[PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks

[Biju <biju.das.au@xxxxxxxxx>]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Add support for parent mod clock to register core clocks that has a
parent module clock on the Renesas RZ/G3E SoC (eg: GPT has two clocks
bus clock and core clock. The core clock is controlled by the bus
clock).

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
 drivers/clk/renesas/rzv2h-cpg.c | 11 +++++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 22 +++++++++++++++++-----
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 8511b7154e90..43fd3fadc5f7 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -823,6 +823,17 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
 	}
 
 	priv->clks[id] = clock->hw.clk;
+	if (mod->child_name) {
+		WARN_DEBUG(mod->child >= priv->num_core_clks);
+		WARN_DEBUG(PTR_ERR(priv->clks[mod->child]) != -ENOENT);
+
+		clk = rzv2h_cpg_mod_status_clk_register(priv, mod->child_name, mod->name, 1, 1,
+							FIXED_MOD_CONF_PACK(mod->mon_index,
+									    mod->mon_bit));
+		if (IS_ERR_OR_NULL(clk))
+			goto fail;
+		priv->clks[mod->child] = clk;
+	}
 
 	/*
 	 * Ensure the module clocks and MSTOP bits are synchronized when they are
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 840eed25aeda..c4205c8fd426 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -235,8 +235,10 @@ enum clk_types {
  */
 struct rzv2h_mod_clk {
 	const char *name;
+	const char *child_name;
 	u32 mstop_data;
 	u16 parent;
+	u16 child;
 	bool critical;
 	bool no_pm;
 	u8 on_index;
@@ -247,11 +249,13 @@ struct rzv2h_mod_clk {
 };
 
 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
-		     _onbit, _monindex, _monbit, _ext_clk_mux_index) \
+		     _onbit, _monindex, _monbit, _ext_clk_mux_index, _childname, _child) \
 	{ \
 		.name = (_name), \
+		.child_name = (_childname), \
 		.mstop_data = (_mstop), \
 		.parent = (_parent), \
+		.child = (_child), \
 		.critical = (_critical), \
 		.no_pm = (_no_pm), \
 		.on_index = (_onindex), \
@@ -262,18 +266,26 @@ struct rzv2h_mod_clk {
 	}
 
 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
 			     _ext_clk_mux_index) \
 	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
-		     _ext_clk_mux_index)
+		     _ext_clk_mux_index, NULL, 0)
+
+#define DEF_MOD_PARENT(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
+			     _child_name, _child) \
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+		     -1, _child_name, _child)
 
 /**
  * struct rzv2h_reset - Reset definitions
-- 
2.43.0