Hi Prabhakar,
On Fri, 8 Aug 2025 at 15:30, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Document the pin and GPIO controller IP for the Renesas RZ/T2H
> (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI
> header file used by both the bindings and the driver.
>
> The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins.
> Both share the same controller architecture; separate compatible
> strings are added for each SoC to distinguish them.
>
> Co-developed-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> ---
> v3->v4:
> - Renamed DT binding file from renesas,rzt2h-pinctrl.yaml to
> renesas,r9a09g077-pinctrl.yaml
> - Updated the title and description to include RZ/N2H SoC
> - Updated description, fixing the information about mux functions
> - Dropped sd0-sd-tmp-pins sub node from sdhi0_sd_pins in the example node
> - Added reviewed-by tag from Rob
Thanks for the update!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> +examples:
> + - |
> + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
> + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> +
> + pinctrl@802c0000 {
> + compatible = "renesas,r9a09g077-pinctrl";
> + reg = <0x802c0000 0x2000>,
> + <0x812c0000 0x2000>,
> + <0x802b0000 0x2000>;
> + reg-names = "nsr", "srs", "srn";
> + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 0 288>;
> + power-domains = <&cpg>;
> +
> + serial0-pins {
> + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
> + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
> + };
> +
> + sd1-pwr-en-hog {
> + gpio-hog;
> + gpios = <RZT2H_GPIO(39, 2) 0>;
> + output-high;
> + line-name = "sd1_pwr_en";
> + };
> +
> + i2c0-pins {
> + pins = "RIIC0_SDA", "RIIC0_SCL";
> + input-enable;
> + };
> +
> + sdhi0_sd_pins: sd0-sd-group {
As per my belated comments on v4, I will drop the sdhi0_sd_pins label...
> + sd0-sd-ctrl-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> + };
> +
> + sd0-sd-data-pins {
... and the "sd0-sd-" prefixes.
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> + };
> + };
> + };
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
> +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
G077
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl for v6.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
