From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Hi all,
This series unifies the OEN handling in the rzg2l pinctrl driver, allowing
support for RZ/G3E SoC and removing redundant code paths for RZ/G2L,
RZ/V2H, and RZ/V2N SoCs. The changes include
- Parameterizing the OEN register offset to support different SoCs.
- Unifying OEN access functions to use a common pin-to-bit mapping.
- Adding support for RZ/G3E SoC with a new PFC_OEN register.
v2->v3:
- Added Reviewed-by tags from Geert.
- Renamed `eth_mode` to `oen` in the rzg2l_pinctrl_reg_cache struct
- Added a if condition to check if the OEN register offset is defined
before reading/writing it in suspend/resume functions
- Updated commit message for patch 2/7
- Added blank line after if condition in rzg2l_read_oen() and
rzg2l_write_oen()
- Grouped oen_pwpr_lock flag with other bools
- Dropped redundant checks for OEN offset in suspend/resume paths
- Updated the commit message for patch 5/7 to reflect the changes
v1->v2:
- patches 1-5 and 7 are new
- patch 6 has been updated to adopt with the new unified OEN handling
Cheers,
Prabhakar
Lad Prabhakar (7):
pinctrl: renesas: rzg2l: Fix invalid unsigned return in
rzg3s_oen_read()
pinctrl: renesas: rzg2l: parameterize OEN register offset
pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping
configurable
pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E
pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}
pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC
pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 195 +++++++++++-------------
1 file changed, 89 insertions(+), 106 deletions(-)
--
2.50.1
