Hi Claudiu,
On Tue, 5 Aug 2025 at 21:18, Claudiu Beznea <claudiu.beznea@xxxxxxxxx> wrote:
> On 04.08.2025 13:00, Geert Uytterhoeven wrote:
> > On Fri, 4 Jul 2025 at 15:43, Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >>
> >> Add MSTOP configuration for all the module clocks on the RZ/G2L
> >> based SoCs (RZ/G2L, RZ/G2LC).
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >
> >> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> >> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> >> @@ -242,163 +242,163 @@ static const struct {
> >> } mod_clks = {
> >> .common = {
> >
> >> DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
> >> - 0x558, 0, 0),
> >> + 0x558, 0, MSTOP(BUS_REG1, BIT(4))),
> >> DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
> >> 0x558, 1, 0),
> >> DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
> >> 0x558, 2, 0),
> >
> > Perhaps these two should have "MSTOP(BUS_REG1, BIT(4))", too?
>
> According to table "Table 42.3 Registers for Module Standby Mode" only bit
> 0 of CPG_CLKON_3DGE maps to bit 4 of CPG_BUS_REG1_MSTOP. There are no hints
Oh, I had completely forgotten about that table, and only looked at the
*_MSTOP register descriptions.
> in the description of CPG_BUS_REG1_MSTOP neither in the description of
> CPG_CLKON_3DGE registers that leads to having bit 4 of CPG_BUS_REG1_MSTOP
> for AXI or ACE clocks as well.
I just found it strange that the AXI or ACE clocks would be the only
clocks without corresponding *_MSTOP bits...
> I tried to play with MSTOP and clocks at runtime to see if there is any
> relation b/w them but can't establish something.
> From software point of view I can add it, it doesn't harm. With this,
> please let me know if you prefer to have it.
OK, then leave it out.
> >> DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
> >> - 0x594, 0, 0),
> >> + 0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
> >> DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
> >> 0x598, 0, 0),
> >
> > "MSTOP(BUS_PERI_CPU, BIT(6))"?
>
> That was a good catch, thank you!
>
> I played with it at runtime and it seems it should be here. It is not
> present in table "Table 42.3 Registers for Module Standby Mode" either. It
> is also valid for RZ/G3S so I'll add it there, too.
OK.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
