Hi Claudiu,
On Fri, 4 Jul 2025 at 15:43, Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Add MSTOP configuration for all the module clocks on the RZ/G2L
> based SoCs (RZ/G2L, RZ/G2LC).
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -242,163 +242,163 @@ static const struct {
> } mod_clks = {
> .common = {
> DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
> - 0x558, 0, 0),
> + 0x558, 0, MSTOP(BUS_REG1, BIT(4))),
> DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
> 0x558, 1, 0),
> DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
> 0x558, 2, 0),
Perhaps these two should have "MSTOP(BUS_REG1, BIT(4))", too?
> DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
> - 0x594, 0, 0),
> + 0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
> DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
> 0x598, 0, 0),
"MSTOP(BUS_PERI_CPU, BIT(6))"?
> DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
> - 0x5a8, 0, 0),
> + 0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
