On Fri, Jul 25, 2025 at 05:26:10PM +0200, Herve Codina wrote: > The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks. > > Add RZ/N1 SoC and family compatible strings. Why? Yes, that's policy, but so far we avoided it on this IP. Perhaps because it is simple enough. So what's different here? > > Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx> > --- > .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml > index ab2afc0e4153..ceb71b5ac688 100644 > --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml > @@ -20,7 +20,13 @@ properties: > pattern: "^gpio@[0-9a-f]+$" > > compatible: > - const: snps,dw-apb-gpio > + oneOf: > + - const: snps,dw-apb-gpio > + - items: > + - enum: > + - renesas,r9a06g032-gpio > + - const: renesas,rzn1-gpio > + - const: snps,dw-apb-gpio > > "#address-cells": > const: 1 > -- > 2.50.1 >
