On Fri, May 30, 2025 at 02:19:12PM +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express > Base Specification 4.0. It is designed for root complex applications and > features a single-lane (x1) implementation. Add documentation for it. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > --- > > Changes in v2: > - update the interrupt names by dropping "int" and "rc" string; due > to this the patch description was adjusted > - added "interrupt-controller" and made it mandatory > - s/clkl1pm/pm/g > - dropped the legacy-interrupt-controller node; with this the gic > interrupt controller node was dropped as well as it is not needed > anymore > - updated interrupt-map in example and added interrupt-controller > - added clock-names as required property as the pm clock is not > handled though PM domains; this will allow the driver to have > the option to request the pm clock by its name when implementation > will be adjusted to used the pm clock > - adjusted the size of dma-ranges to reflect the usage on > SMARC module board > - moved "renesas,sysc" at the end of the node in example to align > with dts coding style > > .../pci/renesas,r9a08g045s33-pcie.yaml | 202 ++++++++++++++++++ > 1 file changed, 202 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > new file mode 100644 > index 000000000000..8ba30c084d1b > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > @@ -0,0 +1,202 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045s33-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# [...] > +examples: > + - | > + #include <dt-bindings/clock/r9a08g045-cpg.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@11e40000 { > + compatible = "renesas,r9a08g045s33-pcie"; > + reg = <0 0x11e40000 0 0x10000>; > + ranges = <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; This 'ranges' property looks bogus. The bitfield specifies that the memory is 64 bit non-prefetchable, which can't be true. - Mani -- மணிவண்ணன் சதாசிவம்
