On Fri, 30 May 2025 14:19:12 +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express > Base Specification 4.0. It is designed for root complex applications and > features a single-lane (x1) implementation. Add documentation for it. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > --- > > Changes in v2: > - update the interrupt names by dropping "int" and "rc" string; due > to this the patch description was adjusted > - added "interrupt-controller" and made it mandatory > - s/clkl1pm/pm/g > - dropped the legacy-interrupt-controller node; with this the gic > interrupt controller node was dropped as well as it is not needed > anymore > - updated interrupt-map in example and added interrupt-controller > - added clock-names as required property as the pm clock is not > handled though PM domains; this will allow the driver to have > the option to request the pm clock by its name when implementation > will be adjusted to used the pm clock > - adjusted the size of dma-ranges to reflect the usage on > SMARC module board > - moved "renesas,sysc" at the end of the node in example to align > with dts coding style > > .../pci/renesas,r9a08g045s33-pcie.yaml | 202 ++++++++++++++++++ > 1 file changed, 202 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
