Hi John,
On Wed, 11 Jun 2025 at 11:02, John Madieu <john.madieu.xa@xxxxxxxxxxxxxx> wrote:
> Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
> IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
> clocks needed by these two GBETH IPs.
>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Tested-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
> {0, 0},
> };
>
> +static const struct clk_div_table dtable_2_100[] = {
> + {0, 2},
> + {1, 10},
> + {2, 100},
> + {0, 0},
> +};
> +
> /* Mux clock tables */
> +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
> +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
> +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rx_clk" };
> +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-tx_clk" };
Please use consistent naming for the external clocks (underscores
vs. dashes). However, both differ from the similar names used on
RZ/V2H and RZ/V2N; perhaps use the naming from the latter instead?
> static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
> static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
>
> @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(4))),
> DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
> BUS_MSTOP(8, BIT(4))),
> + DEF_MOD("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
scripts/checkpatch.pl says:
WARNING: please, no space before tabs
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> + BUS_MSTOP(8, BIT(6))),
Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of DEF_MOD(),
like on RZ/V2H and RZ/V2N?
> DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> BUS_MSTOP(9, BIT(4))),
> DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
The rest LGTM. Note that I don't have access to the Additional Document,
so I couldn't verify all details.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
