Hi Prabhakar,
On Fri, 13 Jun 2025 at 17:29, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> On Thu, Jun 12, 2025 at 3:38 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Document support for Module Standby and Software Reset found on the
> >
> > the Clock Generator and Module Standby and Software Reset
> >
> Ok, I'll amend the commit message as above.
>
> > > Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP
> >
> > Clock Generator and ...
> >
> Ok, I'll amend the commit message as above.
>
> > > is similar to that found on the RZ/T2H SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
> > > @@ -0,0 +1,28 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2025 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* R9A09G087 CPG Core Clocks */
> > > +#define R9A09G087_CLK_CA55C0 0
> > > +#define R9A09G087_CLK_CA55C1 1
> > > +#define R9A09G087_CLK_CA55C2 2
> > > +#define R9A09G087_CLK_CA55C3 3
> > > +#define R9A09G087_CLK_CA55S 4
> > > +#define R9A09G087_CLK_CR52_CPU0 5
> > > +#define R9A09G087_CLK_CR52_CPU1 6
> > > +#define R9A09G087_CLK_CKIO 7
> > > +#define R9A09G087_CLK_PCLKAH 8
> > > +#define R9A09G087_CLK_PCLKAM 9
> > > +#define R9A09G087_CLK_PCLKAL 10
> > > +#define R9A09G087_CLK_PCLKGPTL 11
> > > +#define R9A09G087_CLK_PCLKH 12
> > > +#define R9A09G087_CLK_PCLKM 13
> > > +#define R9A09G087_CLK_PCLKL 14
> >
> > The RZ/T2H DT bindings file lacks PCLKL, which was probably a harmless
> > oversight (it can always be added later), as it does exist on RZ/T2H,
> > too, according to the documentation.
> >
> > However, given drivers/clk/renesas/r9a09g077-cpg.c has
> > LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKM,
> > using R9A09G087_CLK_PCLKL will lead to wrong results.
> >
> > So either you want to add R9A09G077_CLK_PCLKL and update
> > LAST_DT_CORE_CLK first, or set LAST_DT_CORE_CLK to R9A09G087_CLK_PCLKL
> > in this patch.
> >
> Actually I already have a patch which includes a couple of fixes and
> to the orignal bring up series for T2H + I2C support which adds
> R9A09G077_CLK_PCLKL and updates LAST_DT_CORE_CLK. I intend to send
> them when the base patches are accepted. As there are no users for
> PCLKL in the bringup series this won't cause any issues. Is that OK
> with you?
Please include that fix in your v2 series, to avoid any possible
issues with using R9A09G087_CLK_PCLKL.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
