Hi Geert,
Thank you for the review.
On Thu, Jun 12, 2025 at 2:48 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, 9 Jun 2025 at 16:03, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Commit bc4d25fdfadf ("clk: renesas: rzv2h: Add support for dynamic
> > switching divider clocks") missed setting the `CLK_SET_RATE_PARENT`
> > flag when registering ddiv clocks.
> >
> > Without this flag, rate changes to the divider clock do not propagate
> > to its parent, potentially resulting in incorrect clock configurations.
> >
> > Fix this by setting `CLK_SET_RATE_PARENT` in the clock init data.
> >
> > Fixes: bc4d25fdfadfa ("clk: renesas: rzv2h: Add support for dynamic switching divider clocks")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> i.e. will queue in renesas-clk for v6.17, unless you think it deserves
> to be fast-tracked as a fix (issue present since v6.12).
>
I think we can live with this being applied to v6.17. I noticed this
only when adding XSPI support.
Cheers,
Prabhakar
