> -----Original Message----- > From: Prabhakar <prabhakar.csengg@xxxxxxxxx> > Sent: 09 June 2025 23:56 > Subject: [PATCH v7 0/9] drm: renesas: rz-du: mipi_dsi: Prepare driver to support RZ/V2H(P) SoC > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Hi All, > > This patch series prepares the MIPI DSI driver to support the Renesas > RZ/V2H(P) SoC. These patches were originally part of series [0], but I have split them into two parts > to make them easier to review and merge. > > v6->v7: > - Rebased the changes on drm-misc/next > - Dropped DU patches as they are already applied > - Fixed revie comments from Laurent > - Dropped patch 12/12 from v6 "drm: renesas: rz-du: mipi_dsi: Add > support for LPCLK clock handling" as suggested by Laurent > > v5->v6: > - Added reviewed tag from Biju and Laurent > - Updated commit messages > - Dropped parentheses around the calculation > - Added min_dclk above max_dclk in rzg2l_mipi_dsi_hw_info > - Renamed dphy_late_init to dphy_startup_late_init > > v4->v5: > - Split up the series > - Added Reviewed-by tag from Biju > - Dropped feature flags for reset and LPCLK > - Patch 07/12 is new. > > v3->v4: > - Corrected parameter name in rzv2h_dsi_get_pll_parameters_values() > description freq_millihz > - Used MILLI instead of KILO > - Made use of mul_u32_u32() for multiplication > - In rzv2h_dphy_find_ulpsexit() made the array static const. > > v2->v3: > - Update the commit message for patch 1/15 to clarify the purpose > of `renesas-rzv2h-dsi.h` header > - Used mul_u32_u32() in rzv2h_cpg_plldsi_div_determine_rate() > - Replaced *_mhz to *_millihz for clarity > - Updated u64->u32 for fvco limits > - Initialized the members in declaration order for > RZV2H_CPG_PLL_DSI_LIMITS() macro > - Used clk_div_mask() in rzv2h_cpg_plldsi_div_recalc_rate() > - Replaced `unsigned long long` with u64 > - Dropped rzv2h_cpg_plldsi_clk_recalc_rate() and reused > rzv2h_cpg_pll_clk_recalc_rate() instead > - In rzv2h_cpg_plldsi_div_set_rate() followed the same style > of RMW-operation as done in the other functions > - Renamed rzv2h_cpg_plldsi_set_rate() to rzv2h_cpg_pll_set_rate() > - Dropped rzv2h_cpg_plldsi_clk_register() and reused > rzv2h_cpg_pll_clk_register() instead > - Added a guard in renesas-rzv2h-dsi.h header > - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK() > - Renamed plleth_lpclk_div4 -> cdiv4_plleth_lpclk > - Renamed plleth_lpclk -> plleth_lpclk_gear > - Collected reviewed tag from Krzysztof for patch 3/15 > - Dropped !dsi->info check in rzg2l_mipi_dsi_probe() as it > is not needed. > - Simplified V2H DSI timings array to save space > - Switched to use fsleep() instead of udelay() > > v1->v2: > - Rebased the changes on top of v6.15-rc1 > - Kept the sort order for schema validation > - Added `port@1: false` for RZ/V2H(P) SoC > - Added enum for RZ/V2H as suggested by Krzysztof as the list > will grow in the future (while adding RZ/G3E SoC). > - Added Reviewed-by tag from Biju and Krzysztof. > - Replaced individual flags as reset flag > - Dropped unused macros > - Added missing LPCLK flag to rzvv2h info > - Dropped FCP and VSP documentation patch and sent them separately > > Cheers, > Prabhakar > > Lad Prabhakar (9): > drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range > drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation > drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation > drm: renesas: rz-du: mipi_dsi: Add OF data support > drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for > RZ/V2H(P) > drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency > calculations > drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support > drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for > RZ/V2H(P) > drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring > VCLK and mode validation > > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 151 +++++++++++++----- > .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 2 - > 2 files changed, 114 insertions(+), 39 deletions(-) > > -- > 2.49.0 Applied to drm-misc-next Thanks, Biju
