Hi Prabhakar,
On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
> the list of blocks added:
> - EXT CLKs
> - 4X CA55
> - SCIF
> - CPG
> - GIC
> - ARMv8 Timer
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/N2H SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#define RZN2H_PINS_PER_PORT 8
> +
> +/*
> + * Create the pin index from its bank and position numbers and store in
> + * the upper 16 bits the alternate function identifier
> + */
> +#define RZN2H_PORT_PINMUX(b, p, f) ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> +
> +/* Convert a port and pin label to its global pin index */
> +#define RZN2H_GPIO(port, pin) ((port) * RZN2H_PINS_PER_PORT + (pin))
These 3 defines belong in the (future) patch that adds the pinctrl node.
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
Thanks, this brought to my attention that the node in the posted RZ/T2H
patch is wrong ;-)
> + };
> +};
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
