On Wed, Jun 11, 2025 at 11:39:27AM +0200, Wolfram Sang wrote: > From: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx> > > Available in RZ/G3S and G3E SoCs. The G3S has 17 interrupts, the G3E 16 > with the "HDR exit" interrupt missing. This interrupt is put to the end > of the list, so we can handle the difference using "minItems" instead of > defining a separate interrupt list per SoC. > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx> > Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> > --- > > Tommaso also did a version with two interrupt lists and using 'oneOf'. I > prefer this version but maybe the other one is preferred upstream? > > .../devicetree/bindings/i3c/renesas,i3c.yaml | 186 ++++++++++++++++++ > 1 file changed, 186 insertions(+) > create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml > > diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml > new file mode 100644 > index 000000000000..e6e6c57bb56c > --- /dev/null > +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml > @@ -0,0 +1,186 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas I3C Bus Interface > + > +maintainers: > + - Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> > + - Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx> > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a08g045-i3c # RZ/G3S > + - renesas,r9a09g047-i3c # RZ/G3E > + - const: renesas,i3c > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: Non-recoverable internal error interrupt > + - description: Normal transfer error interrupt > + - description: Normal transfer abort interrupt > + - description: Normal response status buffer full interrupt > + - description: Normal command buffer empty interrupt > + - description: Normal IBI status buffer full interrupt > + - description: Normal Rx data buffer full interrupt > + - description: Normal Tx data buffer empty interrupt > + - description: Normal receive status buffer full interrupt > + - description: START condition detection interrupt > + - description: STOP condition detection interrupt > + - description: Transmit end interrupt > + - description: NACK detection interrupt > + - description: Arbitration lost interrupt > + - description: Timeout detection interrupt > + - description: Wake-up condition detection interrupt > + - description: HDR Exit Pattern detection interrupt > + minItems: 16 > + > + interrupt-names: > + items: > + - const: ierr > + - const: terr > + - const: abort > + - const: resp > + - const: cmd > + - const: ibi > + - const: rx > + - const: tx > + - const: rcv > + - const: st > + - const: sp > + - const: tend > + - const: nack > + - const: al > + - const: tmo > + - const: wu > + - const: exit > + minItems: 16 > + > + clocks: > + oneOf: > + - items: > + - description: APB bus clock > + - description: transfer clock > + - items: > + - description: APB bus clock > + - description: SFRs clock > + - description: transfer clock > + > + clock-names: > + oneOf: > + - items: > + - const: pclk > + - const: tclk > + - items: > + - const: pclk > + - const: pclkrw > + - const: tclk Suggested clock name is, apb, trans, srfs. Needn't clk surfix and provide meanful name. > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: Reset signal > + - description: APB interface reset signal/SCAN reset signal > + > + reset-names: > + items: > + - const: presetn > + - const: tresetn the same here: per, apb > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clock-names > + - clocks > + - power-domains > + - resets > + - reset-names > + > +allOf: > + - $ref: i3c.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a08g045-i3c > + then: > + properties: > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + interrupts: > + minItems: 17 > + interrupt-names: > + minItems: 17 > + > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a09g047-i3c > + then: > + properties: > + clocks: > + minItems: 3 > + clock-names: > + minItems: 3 > + interrupts: > + maxItems: 16 > + interrupt-names: > + maxItems: 16 > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r9a08g045-cpg.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + i3c@1005b000 { > + compatible = "renesas,r9a08g045-i3c", "renesas,i3c"; > + reg = <0x1005b000 0x1000>; > + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, > + <&cpg CPG_MOD R9A08G045_I3C_TCLK>; > + clock-names = "pclk", "tclk"; > + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ierr", "terr", "abort", "resp", > + "cmd", "ibi", "rx", "tx", "rcv", > + "st", "sp", "tend", "nack", > + "al", "tmo", "wu", "exit"; > + resets = <&cpg R9A08G045_I3C_PRESETN>, > + <&cpg R9A08G045_I3C_TRESETN>; > + reset-names = "presetn", "tresetn"; > + power-domains = <&cpg>; > + #address-cells = <3>; > + #size-cells = <0>; I prefer put #address-cells and #size-cells after reg Frank > + }; > +... > -- > 2.47.2 >
