On Wed, Jun 04, 2025 at 10:40:25AM +0200, Geert Uytterhoeven wrote:
> Hi Marek,
>
> Thanks for your patch!
>
> On Sat, 31 May 2025 at 00:55, Marek Vasut
> <marek.vasut+renesas@xxxxxxxxxxx> wrote:
> > Add the ability to enable optional slot clock into the pwrctrl driver.
> > This is used to enable slot clock in split-clock topologies, where the
> > PCIe host/controller supply and PCIe slot supply are not provided by
> > the same clock. The PCIe host/controller clock should be described in
> > the controller node as the controller clock, while the slot clock should
> > be described in controller bridge/slot subnode.
> >
> > Example DT snippet:
> > &pcicontroller {
> > clocks = <&clk_dif 0>; /* PCIe controller clock */
> >
> > pci@0,0 {
> > #address-cells = <3>;
> > #size-cells = <2>;
> > reg = <0x0 0x0 0x0 0x0 0x0>;
> > compatible = "pciclass,0604";
> > device_type = "pci";
> > clocks = <&clk_dif 1>; /* PCIe slot clock */
>
> I assume this should be documented in
> dtschema/schemas/pci/pci-bus-common.yaml, too?
You are right.
>
> > vpcie3v3-supply = <®_3p3v>;
> > ranges;
> > };
> > };
> >
> > Example clock topology:
> > ____________ ____________
> > | PCIe host | | PCIe slot |
> > | | | |
> > | PCIe RX<|==================|>PCIe TX |
> > | PCIe TX<|==================|>PCIe RX |
> > | | | |
> > | PCIe CLK<|======.. ..======|>PCIe CLK |
> > '------------' || || '------------'
> > || ||
> > ____________ || ||
> > | 9FGV0441 | || ||
> > | | || ||
> > | CLK DIF0<|======'' ||
> > | CLK DIF1<|==========''
> > | CLK DIF2<|
> > | CLK DIF3<|
> > '------------'
> >
> > Reviewed-by: Anand Moon <linux.amoon@xxxxxxxxx>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
>
> > --- a/drivers/pci/pwrctrl/slot.c
> > +++ b/drivers/pci/pwrctrl/slot.c
>
> > @@ -30,6 +31,7 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
> > {
> > struct pci_pwrctrl_slot_data *slot;
> > struct device *dev = &pdev->dev;
> > + struct clk *clk;
> > int ret;
> >
> > slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL);
> > @@ -50,6 +52,13 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
> > goto err_regulator_free;
> > }
> >
> > + clk = devm_clk_get_optional_enabled(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + ret = dev_err_probe(dev, PTR_ERR(clk),
> > + "Failed to enable slot clock\n");
> > + goto err_regulator_disable;
> > + }
>
> You are adding this block in the middle of the regulator handling.
> Please move it below, under the devm_add_action_or_reset() call
> (which is handled wrong, I have sent a patch[1]).
>
Good catch!
- Mani
--
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