Hello all,
The DWC PCIe controller driver currently does not follow the PCIe
specification with regards to the delays after link training, before
sending out configuration requests. This series fixes this.
At the same time, PATCH 3/7 addresses a regression where a Plextor
NVMe drive fails to be configured correctly. With this series, the
Plextor NVMe drive works once again.
Kind regards,
Niklas
Changes since v3:
-Move LINK_WAIT_MAX_RETRIES and LINK_WAIT_SLEEP_MS to pci.h (Mani)
-Only wait PCIE_RESET_CONFIG_WAIT_MS if > 5 GT/s (Mani)
-Fix nit in commit log (Mani)
Niklas Cassel (7):
PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to
PCIE_RESET_CONFIG_WAIT_MS
PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
up
PCI: Move link up wait time and max retries macros to pci.h
PCI: Reduce PCIE_LINK_WAIT_SLEEP_MS
drivers/pci/controller/dwc/pcie-designware.c | 20 +++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.h | 4 ----
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/pci/controller/pcie-rockchip-host.c | 2 +-
drivers/pci/controller/plda/pcie-starfive.c | 2 +-
drivers/pci/pci.h | 18 +++++++++--------
7 files changed, 30 insertions(+), 18 deletions(-)
--
2.49.0
